In order to remain cost competitive, VLSI and ULSI technologies have been incorporating ever-increasing device densities within their structures. Accordingly, the technology of producing such semiconductor devices has been continually pressured to decrease the surface area required by individual devices in order to increase the corresponding device densities. However, due to the fact that existing device densities are already extremely high, the absolute physical limits will soon be reached in the conventional two-dimensional approach to semiconductor device design. This is particularly true with storage capacitors since the amount of charge necessary to send signals is limited by the presence of environmental particulate radiation inherent within the fabrication materials. Thus, the ability to reduce the surface area utilized by a storage capacitor has been severely restricted. However, the size of the storage capacitors has been decreased due to two significant advances, namely 1) decreases in the thickness of capacitor materials and 2) utilization of three-dimensional designs in which the capacitor memory cell has been altered to provide the capacitor in a vertical dimension. Thus, improved semiconductor technology requires design and process techniques capable of forming three-dimensional structural features which are measured in tens of Angstroms (.ANG.) and in which multiple circuit features are provided in the vertical dimensions.
There are a variety of three-dimensional semiconductor designs known in the art today, for example, Kendall et al. U.S. Pat. No. 3,962,713, describes a three-dimensional capacitor structure formed by a series of vertical fins in the surface of a semiconductor substrate. The fins are oxided and coated with a conductor to form the capacitor. In addition, U.S. Pat. No. 5,160,987 issued to Pricer et al. discloses a method of making three-dimensional semiconductor structures, which in one embodiment as shown in FIG. 1, consists of depositing a series of doped layers 10 and undoped layers 12 of polysilicon upon a semiconductor substrate to form a multiplane laminate. A hexagonal pattern of small vertical trenches extending through the laminate are formed and then an isotropic etch, which preferentially reacts with the lightly doped silicon, is applied to etch the lightly doped silicon thereby exposing the highly doped polysilicon and forming a plurality of trenches 14 in the laminate. Next, by utilizing a blocking mask one or more capacitor islands are formed on the substrate. A thin capacitor dielectric layer is formed by chemically depositing a thin oxynitride dielectric layer 16 of about 150.ANG. upon the exposed surfaces of the highly doped polysilicon. Next, boron doped polysilicon 18 is conformally deposited within the trenches in the laminate, thereby forming a storage capacitor extending in the vertical direction which covers a minimal surface area of the semiconductor substrate.
Accordingly, there exists a need for an exacting method of forming a thin capacitor dielectric evenly over intricate surfaces of three-dimensional shaped silicon structures. However, formation of such capacitor dielectrics poses various problems. In this regard much of the dielectric material must enter through very narrow orifices and yet must still be uniformly distributed over a large cavernous surface. In addition, due to the intricate nature of the three-dimensional structures, the silicon structures are often fragile and as such susceptible to damage from many common processing techniques, in particular from cleaning processes. Furthermore, due to the ever decreasing thickness of the dielectric materials and demand for increased device densities the resulting orifices and cavernous surfaces of the three-dimensional structures are likewise decreasing. Therefore, many techniques for forming oxynitride layers may be inappropriate because the resulting film's thickness may so fill the cavern that a uniform etch back does not occur. In particular, chemical vapor deposition of such materials is often inappropriate for this very reason. In addition, many methods of forming oxynitride films result in a film having nitrogen pile up at the silicon/silicon oxide interface and/or the silicon oxide surface. This nitrogen pile up tends to generate trapped charges in the insulator, thus, making it undesirable for application within a storage capacitor.
It is therefore an object of the present invention to provide a method for forming a thin capacitor dielectric in the form of a uniform oxynitride layer which utilizes only rapid thermal processing techniques. It is a further object of the present invention to provide such a method which is more efficient, having fewer processing steps and a shorter cycle time. It is a further object to produce a capacitor dielectric which is capable of being formed evenly over three-dimensional silicon structures and which may be utilized with such structures without causing damage thereto. It is a further object of the present invention to employ a process which allows exacting control over film thickness. It is a further object of the present invention to create a uniform oxynitride film which provides superior capacitance characteristics. It is a further object of the present invention to create a uniform oxynitride film less susceptible to formation of trapped charges or current leakage.